Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2000-04-04
2003-02-04
Nguyen, Nam (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S297010
Reexamination Certificate
active
06514393
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of flanges that are used to hold items in electrochemical reactors for electroplating and electropolishing operations. More specifically, the flange contains an inflatable bladder that can be selectively inflated and deflated to vary the electric field at the wafer during electrolysis for more uniform thickness control with applicability in making thin films for use in integrated circuits, as well as electronic memory storage devices.
2. Statement of the Problem
Integrated circuits are formed on wafers by well known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well known etching technologies and subsequent deposition steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metalization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. Some integrated circuit manufacturers are investigating electrodeposition techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers have traditionally been made of aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology has demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
Copper damascene circuits are produced by initially forming trenches and other embedded features in a wafer, as needed for circuit architecture. These trenches and embedded features are formed by conventional photolithographic processes. A barrier layer, e.g., of silicon nitride, is next deposited. An initial seed or strike layer about 125 nm thick is then deposited by a conventional vapor deposition technique, and this seed layer is typically a thin conductive layer of copper or tungsten. The seed layer is used as a base layer to conduct current for electroplating thicker films. The seed layer functions as the cathode of the electroplating cell as it carries electrical current between the edge of the wafer and the center of the wafer including fill of embedded structures, trenches or vias. The final electrodeposited thick film should completely fill the embedded structures, and it should have a uniform thickness across the surface of the wafer.
Generally, in electroplating processes, the thickness profile of the deposited metal is controlled to be as uniform as possible. This uniform profile is advantageous in subsequent etchback or polish removal steps. Prior art electroplating techniques are susceptible to thickness irregularities. Contributing factors to these irregularities are recognized to include the size and shape of the electroplating cell, electrolyte depletion effects, hot edge effects and the terminal effect.
For example, because the seed layer is initially very thin, the seed layer has a significant resistance radially from the edge to the center of the wafer. This resistance causes a corresponding potential drop from the edge where electrical contact is made to the center of the wafer. Thus, the seed layer has a nonuniform initial potential that is more negative at the edge of the wafer. The associated deposition rate tends to be greater at the wafer edge relative to the interior of the wafer. This effect is known as the terminal effect.
One solution to the end effect would be to deposit a thicker seed layer having less potential drop from the center of the wafer to the edge, however, thickness uniformity of the final metal layer is also impaired if the seed layer is too thick.
FIG. 1
shows a prior art seed layer
100
made of copperformed atop barrier layer
102
and a dielectric wafer
104
. A trench or via
106
has been cut into wafer
104
. Seed layer
100
thickens in mouth region
108
with thinning towards bottom region
110
. The thickness of seed layer
100
is a limiting factor on the ability of this layer to conduct electricity in the amounts that are required for electroplating operations. Thus, during electrodeposition, the relatively thick area of seed layer
100
at mouth region
108
grows more rapidly than does the relatively thin bottom region
110
with the resultant formation of a void or pocket in the area of bottom region
110
once mouth region
108
is sealed.
FIG. 2
shows an ideal seed layer
200
made of copper formed atop barrier layer
202
and a dielectric wafer
204
. A trench or via
206
has been cut into wafer
204
. Ideal seed layer
200
has three important properties:
1. Good uniformity in thickness and quality across the entire horizontal surface
208
of wafer
204
.;
2. Excellent step coverage exists in via
206
consisting of continuous conformal amounts of metal deposited onto the sidewalls; and
3. In contrast to
FIG. 1
, there is minimal necking in the mouth region
210
.
It is difficult or impossible to obtain these properties in seed layers having a thickness greater than about 120 nm to 130 nm.
The electroplating of a thicker copper layer should begin with a layer that approximates the ideal seed layer
200
shown in FIG.
2
. The electroplating process will exacerbate any problems that exist with the initial seed layer due to increased deposition rates in thicker areas that are better able to conduct electricity. The electroplating process must be properly controlled or else thickness of the layer will not be uniform, there will develop poor step coverage, and necking of embedded structures can lead to the formation of gaps of pockets in the embedded structure.
A significant part of the electroplating process is the electrofilling of embedded structures. The ability to electrofill small, high aspect ratio features without voids or seams is a function of many parameters. These parameters include the plating chemistry; the shape of the feature including the width, depth, and pattern density; local seed layer thickness; local seed layer coverage; and local plating current. Due to the requisite thinness of the seed layers, a significant potential difference exists between the center of a wafer and the edges of a wafer. Poor sidewall coverage in embedded structures, such as trench
106
in
FIG. 1
, develops higher average resistivity for current traveling in a direction that is normal to the trench. Due to these factors in combination, there is a finite range of current densities over which electrofilling can be performed.
Manufacturing demands are trending towards circumstances that operate against the goal of global electrofilling of embedded structures and thickness uniformity. Industry trends are towards thinner seed films, larger diameter wafers, increased pattern densities, and increased aspect ratio of circuit features. The trend towards thinner seed layers is required to compensate for an increased percentage of necking in smaller structures, as compared to larger ones. For example,
FIG. 3
shows a comparison between etched versus seeded features for a HCM PVD process. A 45° line is drawn to show no necking, but the data shows necking as the seeded feature width rolls downward in the range from 0.3 &mgr;m to 0.15 &mgr;m.
Regarding the trend towards larger diameter wafers, it is generally understood that the deposition rate, as measured by layer thickness, can be maintained by scaling total current through the electrochemical reactor in proportion to the increased surface area of the larger wafer. Thus, a 300 mm wafer requires 2.25 times more current than does a 200 mm wafer. Electroplating operations are normally performed by using a clamshell wafer holder that contacts the wafer only at its outer radius. Due to this mechanical arrangem
Contolini Robert J.
McCutcheon Andrew J.
Nguyen Nam
Novellus Systems Inc.
Patton & Boggs LLP
Smith-Hicks Erica
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