Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-04-27
2001-04-03
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S201000, C327S215000
Reexamination Certificate
active
06211713
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to digital latches, and in particular to a method and system for altering the amount of feedback within a latch in conformity with actual operating requirements. Still more particularly, the present invention relates to a method and system which varies feedback within CMOS latch circuits to provide an optimal balance between functionality and performance of the circuit.
DESCRIPTION OF THE RELATED ART
Digital logic systems may be generally categorized as either combinatorial or sequential. A combinatorial circuit consists of logic gates whose outputs at any time are determined directly from the values of the present inputs. A combinational circuit performs a specific information processing operation which can be specified logically by a set of Boolean expressions. Sequential circuits employ storage elements called flip-flops in addition to the logic gates. Their outputs are a function of the inputs and the state of the storage elements. The state of the storage elements, in turn, is a function of previous inputs. As a consequence, the outputs of a sequential circuit depend not only on the present values of the inputs, but also on past inputs, and the circuit behavior must be specified by a time sequence of inputs and internal states.
While every digital system is likely to have a combinational circuit, most systems encountered in practice include storage elements such as latches. Examples of digital circuits employing latches include registers, counters, static memory arrays, etc.
Referring to
FIGS. 1A and 1B
, a conventional CMOS latch circuit
100
and its accompanying timing diagram
115
are depicted. A storage node
102
within latch circuit
100
is comprised of a latch inverter
104
and a feedback inverter
106
. Latch circuit
100
is configured in a cross-coupled configuration in which the output of latch inverter
104
is coupled to the input of feedback inverter
106
at latch node
114
. A feedback node
112
is the common point where the output of feedback inverter
106
is coupled to the input of latch inverter
104
. Data stored at any given point in time at feedback node
112
is buffered from input data by clocked input inverter
108
and from the output of latch circuit
100
by output inverter
110
. Timing diagram
115
of
FIG. 1B
illustrates the operation of latch circuit
100
with respect to the relative signal levels existing within the circuit.
CMOS latches, such as CMOS latch
100
, are utilized to store digital data in the form of a logical “1” or a logical “0”. When clock input
116
is asserted, latch circuit
100
becomes either “transparent” or “opaque”. “Transparent” means that the latch is open and a data bit can pass from input
118
to feedback node
112
. “Opaque” means that latch circuit
100
is closed and output
120
holds the last data that passed through while the latch was transparent.
The central components of storage node
102
are a pair of cross-coupled inverters
104
and
106
. Latch inverter
104
has its output port connected to latch node
114
and is referred to as the “latch inverter”. Inverter
106
has its output connected to feedback node
112
and is known as the “feedback inverter”. This cross-coupled pair of inverters is incorporated in latch circuit
100
at feedback node
112
as portrayed in FIG.
1
. An output node
120
of CMOS latch
100
is the buffered output of output inverter
110
. Clocked inverter
108
has an input/output clock control means. Clocked inverter
108
is a tri-state inverter with its control inputs coupled to a system clock
116
(not depicted), and the inverse of the system clock
122
.
Conventionally, a feedback inverter such as feedback inverter
106
is designed to provide enough feedback to store a data input accurately in an electrically noisy environment. The amount of feedback provided by feedback inverter
106
must not, however, be so great that new data is blocked from access into CMOS latch
100
. Thus, there is always an engineering tradeoff between functionality and performance.
Variable environmental and operational conditions often dictate that a designer design for the worst-case situation. To ensure adequate long-term reliability, circuits are subjected to extremely high voltages and temperatures during manufacturing tests such as burn-in testing or Dynamic Voltage Stress (DVS) . The extreme conditions experienced by the tested circuitry are designed to accelerate early failures by subjecting the circuitry to conditions which are rarely ever encountered when the circuit is actually operated. These conditions aggravate leakage and noise, thus requiring the designer to implement a greater amount of feedback to permit the circuit to function during testing. Performance is of secondary importance to functionality during these manufacturing testing regimens. In normal operation, however, performance, particularly with respect to circuit speed, is also of paramount importance. Since the circuitry has been designed with an amount of feedback necessary to counteract the unrealistic environments utilized during testing, performance and speed are degraded by excessive feedback during normal circuit operations.
Modern circuits have much higher operating speeds and lower operating voltages than previous generations of integrated circuits. A current standard for state-of-the-art integrated circuits is 1.8 volts. Thus the effect of feedback on the performance a CMOS latch, in terms of switching speed, is increasingly pronounced.
It would therefore be desirable to provide a controllable feedback source for a CMOS latch. Further, it would be desirable to be able to control the amount of feedback in a CMOS latch such that functionality during testing is preserved, and performance during normal operation is optimized.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide improved digital latches.
It is another object of the present invention to provide a method and system for altering the amount of feedback within a latch in conformity with actual operating requirements.
It is still another object of the present invention to provide a method and system which varies feedback within CMOS latch circuits to provide an optimal balance between functionality and performance of the circuit.
The foregoing objects are achieved as is now described. An improved latch circuit having a dynamically adjustable internal feedback level is disclosed. The improved latch circuit includes a latch inverter and a feedback inverter cross-coupled with the latch inverter. A controllable supplemental feedback inverter is connected in parallel with the feedback inverter to provide a controllable level of feedback to the latch inverter. An independently selectable control signal enables or disables the controllable feedback inverter in conformity with a need for more or less feedback, such that the internal feedback level may provide optimal functionality and performance of the latch circuit.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5467038 (1995-11-01), Motley et al.
patent: 5767716 (1998-06-01), Ko
patent: 5769283 (1998-08-01), Martin
patent: 5825225 (1998-10-01), Sugisawa et al.
“Method and Apparatus to Control Noise In a Dynamic Circuit,” Serial No. 09/041,982; filed Mar. 13, 1998, pp. 1-29.
Cunningham Terry D.
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Nguyen Long
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