Adjustable depth/width FIFO buffer for variable width data trans

Details Adjustable depth/width FIFO buffer for variable width data trans Adjustable depth/width FIFO buffer for variable width data trans

1994-12-16

1997-09-30

Eng, David Y.

Boots, shoes, and leggings

364939, 3642545, 364239, G06F 1300

Patent

active

056733968

ABSTRACT:
An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.

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