Wave transmission lines and networks – Coupling networks – Delay lines including long line elements
Reexamination Certificate
2000-04-26
2004-05-11
Lee, Benny (Department: 2817)
Wave transmission lines and networks
Coupling networks
Delay lines including long line elements
C333S156000
Reexamination Certificate
active
06734757
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to delay lines and more specifically to a minimum area adjustable delay line structure useful in providing phase control in high frequency circuit applications.
The prior art teaches miniature delay line circuits with multiple delay outputs as represented in U.S. Pat. No. 4,641,114 and U.S. Pat. No. 4,942,373. Both patents use a stacked packaging configuration employing substrates with delay lines formed thereon. The '114 patent describes delay line circuit assemblies with each assembly consisting of a thick film delay line formed on a dielectric substrate and having a plurality of conductive pads mounted along the edge thereof The delay line is a spiral coil conductor having its opposite ends connected to separate contact pads. Each delay circuit has an initial layer of a solid sheet conductive material, a first layer of dielectric material superimposed over the solid conductor sheet, the spiral coil conductor formed on the dielectric material, and a second sheet of dielectric material covering the spiral conductor. The solid sheet conductive layers are connected to a common conductive pad that may be connected to a common ground. The delay circuit assemblies are stacked one on top of the other with the spiral conductors within each of the delay line circuit assemblies being connected to one another in series. Leads extend from the stack of delay circuit assemblies with each lead being in electrical contact with respective conductive pads. The stacked assemblies and a portion of the leads are coated in an encapsulating dielectric material. Different delay times may be achieved by tapping different leads of the delay line assembly.
The '373 patent describes multi-layered, thick/thin film delay lines which are tailored to provide line impedances yielding unit delays of 1 to 10 nanoseconds. One of the described embodiments comprises a modularly constructed assembly providing for high-density packaging of a number of transmission lines in a single component to achieve multiple outputs or long delay values. The assembly is formed on a fiber/resin substrate on which is formed a serpentine delay line having right and left hand sides. Formed over the lowermost delay line are successively a screen printed polyamide dielectric layer, an evaporated copper ground plane layer and a screen printed polyamide dielectric layer. Lastly, a second transmission line layer similar to the lowermost transmission line is formed on the upper dielectric layer. Contact pads are provided on the ends of the respective transmission lines. Additional contact pads are electrically connected to the ground plane. Contact pins are soldered/bonded to the appropriate contact pads on the lowermost delay line layer. Jumper wires or vias appropriately connect others of the contact pads to the lowermost delay line layer.
One drawback to the above described miniature delay line circuits is the complexity of the manufacturing process. The various layers require individual processing and assembly to produce the delay line circuits. What is needed is an adjustable delay line phase shifter that is simple to produce and occupies a minimum area on a substrate or circuit board.
SUMMARY OF THE INVENTION
Accordingly, the present invention is a minimum area adjustable delay line phase shifter incorporating a microstrip transmission line made up of conductive shapes, such as squares or rectangles with or without beveled corners and the like. The adjustable delay line phase shifter includes a dielectric substrate having an upper surface and a lower surface. A conductive ground layer is deposited on the lower surface of the dielectric substrate. A matrix of conductive elements is deposited on the upper surface of the dielectric substrate in M rows and N columns where M and N are equal to or greater than 2 and having N−1 to (M×N)−1 conductive members electrically connecting from N to (M×N) conductive elements together. A first conductive element acts as an input port and a second conductive element acts as an output port. The preferred embodiment of the invention uses substantially square conductive elements. Alternately, the conductive elements may be substantially rectangular, rectangular with beveled corners, or any geometric or non-geometric shape that does not compromise the overall characteristic impedance of the delay line. Preferably the conductive members are gold ribbons. Alternately, the conductive members may be a plurality of bond wires, such as two or three bond wires connecting two conductive elements. The objects, advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawings.
REFERENCES:
patent: 4641114 (1987-02-01), Person
patent: 4942373 (1990-07-01), Ozawa et al.
patent: 5030932 (1991-07-01), Kameya
patent: 5170140 (1992-12-01), Lowe et al.
patent: 5694134 (1997-12-01), Barnes
patent: 5815050 (1998-09-01), Brooks et al.
Bucher William K.
Gray Francis I.
Lee Benny
Tektronix Inc.
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