Adjustable delay circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

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327276, H03H 1126

Patent

active

060972335

ABSTRACT:
An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.

REFERENCES:
patent: 5453709 (1995-09-01), Tanimoto et al.
patent: 5506534 (1996-04-01), Guo et al.
patent: 5592116 (1997-01-01), Bedouani
patent: 5621360 (1997-04-01), Huang
patent: 5917357 (1999-06-01), Kwon
patent: 5936451 (1999-08-01), Phillips et al.
patent: 6014050 (2000-01-01), McClure
Japanese Patent Abstract No. 08018413 (Takatomo), dated Jan. 19, 1996.
Japanese Patent Abstract No. 4-135311 (Nagashima), dated May 8, 1992.

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