Adjustable clock driver circuit

Details Adjustable clock driver circuit Adjustable clock driver circuit

2005-04-19

2005-04-19

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S148000

Reexamination Certificate

active

06882593

ABSTRACT:
A circuit for generating a clock signal to driver a plurality of memory components in a memory subsystem. The clock driver circuit comprises a clock generator for transmitting a clock signal to drive the plurality of memory components, a memory controller for controlling the plurality of memory components, and an adjustable impedance circuit residing within said memory controller such that the adjustable impedance circuit is programmable in accordance with a control input generated by the memory controller. The clock generator is configured to generate a clock signal with a voltage swing controlled by the impedance of the adjustable impedance circuit.

REFERENCES:
patent: 6192005 (2001-02-01), Lee
patent: 6573746 (2003-06-01), Kim et al.
patent: 20010035768 (2002-11-01), Garlepp et al.
patent: 20030231523 (2003-12-01), Cho et al.
Gabara, T.J., et al., “Digitally Adjustable Resistors in CMOS for High-Performance Applications,” IEEE J. of Solid-State Circuits, vol. 27, No. 8, Aug. 1992, pp. 1176-1185.
PCT International Search Report, International Application No. PCT/US2004/018226, International Filing Date—Mar. 6, 2004, dated Sep. 13, 2004.

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