Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-12-20
1992-06-23
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307291, 307265, 307267, 307605, 328 58, H03K 329, H03K 3017
Patent
active
051245736
ABSTRACT:
A clock chopper/expander circuit 10 includes a reset dominant latch circuit 20 which is set by a CLOCK IN signal 12 and reset by a delayed CLOCK IN signal labelled DELAY 26, provided by an asymmetrical delay circuit 22 which delays the CLOCK IN signal T.sub.D seconds. The delay circuit 22 utilizes an adjustable bias current source 64 to bias a half memory cell 50, which charges up a node 62 according to the write time of the cell 50. A sensing circuit triggers a DELAY transition when node 62 crosses a voltage predetermined by the bias provided to a second half memory cell 52 which is also controlled by the bias current source 64. A multiplexer 24 provides disablement of the clock chopping/expanding function and an OR gate 14 facilitates easy measurement of the actual delay introduced by circuit 22.
REFERENCES:
patent: 4604582 (1986-08-01), Strenkowski
patent: 4726045 (1988-02-01), Caspell et al.
patent: 4851711 (1989-07-01), Chan
patent: 4970418 (1990-11-01), Masterson
IBM Technical Disclosure Bulletin, vol. 30, No. 6, Nov. 1987, entitled "Clock Expander with Mutually Referenced Current Switches" by R. C. Wong.
IBM Technical Disclosure Bulletin, vol. 29, No. 7, Dec. 1986, entitled "Clock Chopper for Complementary-Transistor Switch Arrays", by Y. H. Chan.
IBM Technical Disclosure Bulletin, vol. 31, No. 4, Sep. 1988, entitled "Mutually-Referenced Current Switches", by R. C. Wong.
International Business Machines
Miller Stanley D.
Romanchik Richard A.
Wambach Margaret Rose
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