Adjustable 3D capacitor

Details Adjustable 3D capacitor Adjustable 3D capacitor

2002-04-25

2004-02-10

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Rendering selected devices operable or inoperable

C438S240000, C438S387000, C438S396000, C438S666000

Reexamination Certificate

active

06689643

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to variable capacitors occupying minimum chip real estate.
BACKGROUND OF THE INVENTION
LC or RC matching of networks is critical for some analog or RF circuits. Adjustment of capacitor values after the circuits are already in use is not possible. Once the capacitor value has been pre-set, subsequent fine tuning is not possible and an entirely new mask is needed for the capacitor portions of the circuit. Additionally, conventional flat capacitor designs tend to occupy large amounts of chip real estate, acting as a bottleneck for further circuit densification.
In the pre-integrated circuit era, one of the ways of providing an adjustable capacitor was the layout schematically shown in FIG.
1
. Seen there are four top electrodes
15
that share a common lower electrode
11
. By means of switches
16
the top electrodes can be connected in parallel, as needed to provide a capacitance value between 1 and 9 units between points A and B since, as can be seen, the ratios of the individual top electrode areas are 5:2:1:1.
The present invention discloses how the schematic circuit of
FIG. 1
can be implemented in an integrated circuit, with minimum consumption of chip real estate.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 5,350,705, Brassington et al. show a flat capacitor arrangement with common top plate. Aitken et al. in U.S. Pat. No. 6,088,258 shows a planarized interweave capacitor. In U.S. Pat. No. 5,604,145, Hashizume et al. disclose a planar capacitor process while in U.S. Pat. No. 5,744,385, Hojabri reveals a compensation technique for a parasitic capacitor.
SUMMARY OF THE INVENTION
It has been an object of at least one embodiment of the present invention to provide a capacitor for use in micro-electronic circuits.
Another object of at least one embodiment of the present invention has been that said capacitor be adjustable at the time that said micro-electronic circuits are being manufactured.
Still another object of at least one embodiment of the present invention has been that said capacitor be adjustable at the time that said micro-electronic circuits are being used in the field.
A further object of at least one embodiment of the present invention has been to provide a process for manufacturing said adjustable capacitor.
These objects have been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor.


REFERENCES:
patent: 5172201 (1992-12-01), Suizu
patent: 5350705 (1994-09-01), Brassington et al.
patent: 5604145 (1997-02-01), Hashizume et al.
patent: 5744385 (1998-04-01), Hojabri
patent: 5913126 (1999-06-01), Oh et al.
patent: 6088258 (2000-07-01), Aitken et al.
patent: 6255161 (2001-07-01), Lin
patent: 6268620 (2001-07-01), Ouellet et al.
patent: 6281541 (2001-08-01), Hu
patent: 6391707 (2002-05-01), Dirnecker et al.
patent: 6461911 (2002-10-01), Ahn et al.
patent: 6630380 (2003-10-01), Joy et al.
Wolf, Ph.D., Stanley, “Multlevel-Interconnect Technology for VLSI and ULSI,” Silicon Processing for the VLSI Era—vol. 2: Process Integration, Lattice Press (1990), pp. 189-190, 194-199.

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