Adhesion between dielectric materials

Details Adhesion between dielectric materials Adhesion between dielectric materials

2002-11-27

2004-03-30

Lam, Cathy (Department: 1775)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S753000, C257S759000, C257S760000

Reexamination Certificate

active

06713873

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and, more specifically, to a method of improving adhesion at an interface between dielectric materials, as well as, a structure including an adhesion promoter layer at the interface between dielectric materials.
2. Discussion of Related Art
Gordon Moore first suggested in 1965 that the pace of technology innovation would double the number of transistors per unit area on a chip every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to Moore's Law in improving device density.
Maintaining such an aggressive schedule for each device generation has required continual enhancements at the corresponding technology node. Additive processes using ion implantation, annealing, oxidation, and deposition had to be enhanced to deliver the requisite doping profiles and film stacks. Subtractive processes using photolithography and etch also had to be improved to shrink the features on the chip while maintaining pattern fidelity.
Improving resolution in photolithography to produce a smaller critical dimension (CD) for the features usually decreased the depth of focus (DOF) that was available. However, the smaller DOF could be tolerated if variations in topography were minimized across the chip. Thus, chemical-mechanical polish (CMP) became an enabling technology for both the front-end and the back-end of semiconductor processing.
The scaling down of transistors and wiring to comply with Moore's Law may degrade the performance and reliability of the chip if it is not accomplished properly. For example, the switching speed of the transistors may be adversely impacted if the resistance-capacitance (RC) product delay in the wiring is too large. Resistance may be reduced by using a conductive material with a low resistivity while capacitance may be reduced by using a dielectric material with a low dielectric constant (k). However, adhesion at an interface between two dielectric materials may be inadequate, resulting in poor yield at assembly and packaging from cracking and delamination.
Thus, what is needed is a method of improving adhesion at an interface between dielectric materials, as well as, a structure including an adhesion promoter layer at the interface between dielectric materials.


REFERENCES:
patent: 5442237 (1995-08-01), Hughes et al.
patent: 5552627 (1996-09-01), McCollum et al.
patent: 6111301 (2000-08-01), Stamper
patent: 6249055 (2001-06-01), Dubin
patent: 6323554 (2001-11-01), Joshi et al.

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