Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1999-07-06
2001-11-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S106000, C438S126000, C438S455000, C438S602000, C438S686000, C438S931000, C427S255290
Reexamination Certificate
active
06319757
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the adhesion and/or encapsulation of semiconductor devices or circuits on ceramic substrates, and more particularly to the adhesion and/or encapsulation of silicon carbide semiconductors with metal or alloy contacts and conductors, and metal circuits on AlN substrates.
SiC-based semiconductor devices possess tremendous advantages for high temperature and high power solid state electronics. In addition, these devices offer potential advantages for high frequency and logic circuit applications: e.g., power conversion (mixer diodes, MESFETs), and single chip computers (n-MOS, CMOS, bipolar transistors). Non-volatile random access memory SiC CCDs can hold charge for more than a thousand years thus, for example, making hard disks a thing of the past.
The potential maximum average power, maximum operating temperature, thermal stability, and the reliability of SiC electronics, for example, far exceeds Si or GaAs based electronics. The degree to which these advantages of SiC can be utilized, however, is presently constrained by the thermal stability and electrical properties of the metal/SiC junctions. The primary reasons for this are: (1) the power density of SiC devices is limited by the thermal stability of the ohmic contact junctions, and (2) substantial cooling is required to insure the stability of electrical contact junctions.
For a long time, researchers have been striving without success to develop electrical contacts to silicon carbide to overcome the aforementioned constraints. Until these constraints are removed, SiC devices/circuits offer only marginal, if any, advantages over Si and GaAs. Utilization of the full performance potential of SiC itself (for all devices), requires four types of performance-limiting electrical contacts: (1) ohmic to p-type SiC, (2) ohmic to n-type SiC, (3) rectifying to p-type SiC, and (4) rectifying to n-type SiC.
The value of SiC electronics lies in its potential to extend the capabilities of solid state electronics beyond what is possible with Si or GaAs. Thus, suitable electrical contact characteristics obtained in the laboratory—under low stress conditions—must not drift or degrade, due to changes at the metal/SiC junctions, under actual device operating conditions. This requires two additional attributes of metal/SiC electrical contacts. First, the contact metal must form a junction with SiC that is chemically stable to ~1000° C. (joule heating at high forward current densities in power SiC devices could easily cause metal/SiC junctions to reach such temperatures) or more. Second, the contact metal (or metallization structure) must act as a diffusion barrier to circuit and bonding metals (electrode metals) at the same temperatures. Metal/SiC electrical contacts demonstrated previously do not come close to meeting all these stability requirements.
Commonly-assigned U.S. Ser. No. 08/612,216 filed Mar. 7, 1996 (counterpart PCT application PCT/US97/03497, filed Mar. 4, 1997), which is incorporated herein by reference, however, discloses contacts of all four types which have the requisite attributes. What is needed now is a suitable way to package SiC devices with Os and TiC/WC/W contacts and compatible conductive wires or lines on a suitable substrate, so as to be protected mechanically and chemically over a wide range of conditions. The current state of the art fails to meet this need.
Applicant has learned that a TiC contact on _SiC does not, by itself, form a diffusion barrier to circuit or bonding metals. Appropriate circuit/bonding metals such as W, Pt, Au and Pd, form intermetallics with TiC. These solid state reactions change the composition of the electrical contact junction, thus degrading it.
In a recent study, Tong et. al. (Ref. 1) examined the feasibility of fabricating large area SiC substrates from CVD-grown SiC layers on Si(
100
) substrates via pressure bonding between two thermal oxide layers. The process of Tong et al is as follows: (1) chemical vapor deposition of SiC layer on Si(
100
), (2) thermal oxidation to form a thin layer of SiO2 on SiC layer, (3) fabrication of a separate Si wafer with thicker thermal oxide layer, (4) surface treatments to enhance the subsequent pressure bonding, (5) pressure induced bonding between two thermal oxide layers, (6) high temperature annealing to improve bonding characteristics by densification, (7) lapping (polishing) to remove the oxide layer from the wafer initially with SiC layer, and finally, (8) chemical etching of exposed Si wafer down to SiC layer.
In addition to the complexity of the process of Tong, et al, the bonding between two thermal oxides is undoubtedly hampered by surface roughness, trapped bubbles, outgassing from the thermal oxides, and a thermal expansion coefficient mismatch among Si, SiO2, and SiC (about 20%). Such problems become markedly more detrimental when the operating conditions become harsher. Moreover, Si itself is not suitable for the high temperature (over 250° C. and as high as 115° C.). Harsh environment applications of SiC electronic devices, because of the thermal expansion mismatch, lower thermal conductivity, and lower melting temperature (1412° C.) of Si, will render the device structurally unstable.
In another bonding study (see Ref. 2), several systems-metals (Al, Ni, Ti, and W), polycrystalline silicon, phosphosilicate glass, and SiO2 have been employed to bond polycrystalline SiC slabs together. However, high temperature annealing (1150° C.) under some controlled ambient conditions (e.g. steam with 2% HCl) was required to achieve effective bonding. This anneal temperature is too high in that it exceeds the stability window of conventional Si devices. Problems associated with the surface roughness of the slabs (as in Ref. 3) arise as well. The bonding process using metallic layers at high temperatures can also lead to silicide formation. This is not suitable for SiC devices because, in the anticipated operating ranges (temperature and environment), the metal layer could become unstable and/or the metal layer will be consumed by the very bonding reaction with SiC which will change the characteristics of the SiC device.
In fact, this instability of a metal layer in contact with SiC at high temperatures has been an obstacle to the development of SiC devices that can fully exploit the advantageous properties of SiC for high temperature electronics. Similarly, the reaction bonding with the phosphosilicate glass poses the potential problem of phosphorous incorporation into SiC, which can change the electrical properties of the device. Thus, a need remains for a suitable SiC-to-substrate adhesion system.
The prior art also has not developed a material and/or process which forms a stable, insulating, and adherent high-temperature (T>1000° C.) encapsulation layer on SiC devices and their related components (metallization on SiC die and AlN package substrate, connecting wires, and die insulating material).
For low-temperature electronic devices, the encapsulation layer is readily formed using many different materials and processes. In the 1970's a ceramic system, known as “CERATAB” packaging, was used. (Ref. 4) In more recent years, the encapsulation materials have been silicone with ceramic fillers (Ref. 5), epoxy resins (Ref. 6) and plastics (Ref. 7). A more exotic approach to encapsulation consists of alternating layers of polyamide and ceramic. (Ref. 8) Organic encapsulation materials do not function at high temperatures. The high temperature ceramic materials suffer from high porosity and brittleness problems even if the material itself satisfies the requirement for electrical insulation and high temperature stability.
A recent patent discusses a fabrication process for a ceramic material which consists of zirconia or hafnia powder suspended (encapsulated) in crystalline cordierite (mixture of MgO, CaO and Y
2
O3) glass-ceramic materials. (Ref. 9) Although this patent states that it is suitable in packaging LSI circuits, the process as described, is not in fact, suitable for en
Kwak B. Leo
Parsons James D.
Caldus Semiconductor, Inc.
Lytle Craig P.
Marger & Johnson & McCollom, P.C.
Smith Matthew
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