Addressing unit for a microprogrammed memory

Details Addressing unit for a microprogrammed memory Addressing unit for a microprogrammed memory

1977-06-14

1981-01-27

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 926

Patent

active

042479045

ABSTRACT:
An addressing unit for accessing two sequences of instructions quasi-simultaneously, the two sequences of instructions being prerecorded in a single memory. Addresses for the two sequences appear alternately at the address output of the addressing unit at a predetermined clock rate. During a single clock period, the addressing unit receives data for calculating the next address in the first sequence while it is calculating the address of the next instruction in the second sequence. In the following clock period the addressing unit calculates the address of the next instruction in the first sequence while it is receiving data for calculating the address of the next instruction in the second sequence, and so on. In this manner, the unit is simultaneously receiving data for one sequence and calculating an address for the other sequence.

REFERENCES:
patent: 2866177 (1958-12-01), Steele
patent: 3689895 (1972-09-01), Kitamura
patent: 3956738 (1976-05-01), Tessera
patent: 4001788 (1977-01-01), Patterson et al.
patent: 4025901 (1977-05-01), Bachman et al.
patent: 4050058 (1977-09-01), Garlic
Faix et al., "Increasing the Effective Speed of a Microprogram Store", IBM Tech. Discl. Bull., vol. 16, No. 2, Jul. 1973, pp. 438-440.

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