Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent
1998-10-14
1999-12-28
Nguyen, Tan T.
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
36523006, G11C 800
Patent
active
060090383
ABSTRACT:
In an addressing unit fort reducing a wasteful time created to reach an address latch to attain fast processing, a pre-decoder for pre-decoding an X address and a Y address is provided in a preceding stage to the address latch, the address signal pre-decoded by the pre-docoder is latched in the address latch and the latched address signal is decoded by a decoder. Thus, the pre-docode process can be conducted in the same time period required to latch the address signal in a conventional unit in which the pre-decoder is arranged in a succeeding stage of the address latch circuit, and after the address latching, only the decode process is needed.
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Nguyen Tan T.
United Microelectronics Corporation
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