Addressing technique for providing read, modify and write operat

Details Addressing technique for providing read, modify and write operat Addressing technique for providing read, modify and write operat

1986-06-26

1991-03-19

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1300

Patent

active

050016652

ABSTRACT:
A technique for accomplishing a read, modify and write operation of a memory in a processor in a single cycle of the processor, where a cycle is understood as the time between successive loads of operands to the processor. A memory having two distinct portions of operands is provided wherein the single cycle operations are accomplished by virtually addressing the operands in a serpentine or snake-like configuration. A decoder is provided for efficiently controlling the concurrent reading and writing of operands and controlling the addressing of the memory.

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Driscoll et al., Split Cache with Variable Interleave Boundry, 4/80, IBM Technical Disclosure Bulletin, vol. 22, #11, p. 5183.

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