Boots – shoes – and leggings
Patent
1983-07-01
1987-02-17
Shaw, Gareth D.
Boots, shoes, and leggings
364900, G06F 1300
Patent
active
046444696
ABSTRACT:
When a CPU accesses a memory device, the upper address data of an address signal is transmitted as parallel signals while the upper address data thereof is transmitted as serial signals after parallel-serial conversion. In order to convert the upper address into the serial signals, a parallel-serial converter is disposed on the side of the CPU or on the side of the CPU of an address bus while a serial-parallel converter is disposed on the side of a memory device or on the side of the memory device of an address bus. The signal lines of the address bus can be decreased in number.
REFERENCES:
patent: 3742456 (1973-06-01), McFiggans et al.
patent: 3962682 (1976-06-01), Bennett
patent: 4194243 (1980-03-01), Tsuda
patent: 4298928 (1981-11-01), Etoh et al.
Eakman Christina M.
Shaw Gareth D.
Tokyo Shibaura Denki Kabushiki Kaisha
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