Addressing system for an associative cache memory

Details Addressing system for an associative cache memory Addressing system for an associative cache memory

1983-08-30

1986-12-23

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1208

Patent

active

046316604

ABSTRACT:
A memory system which comprises a mainstore for storing lines of data and a buffer store for storing lines of data that are a subset of the data stored in the main store. The buffer store is comprised of a plurality of associativities. A line of data stored in the buffer having a given address may be stored in any one of the plurality of associativities. A tag store stores a tag for the associativities. A field from a buffer store address is compared with the stored tag in the tag store to produce a data selection signal for selecting from among the plurality of associativities the proper line of data. When the buffer has only two associativities, a bit in the buffer store address which has different values for the two associativities is tested, and thus the proper line of data is selected. The bit position is indicated by a pointer stored in the tag array. A selection of one of two data lines is made prior to a determination of the presence or validity of data in the buffer store.

REFERENCES:
patent: 4045781 (1977-08-01), Levy
patent: 4168541 (1979-09-01), DeKarske
patent: 4381541 (1983-04-01), Baumann
patent: 4400770 (1983-08-01), Chan
patent: 4441155 (1984-04-01), Fletcher

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