Addressing scheme for a double data rate SDRAM

Details Addressing scheme for a double data rate SDRAM Addressing scheme for a double data rate SDRAM

1998-12-03

2000-03-28

Phan, Trong

Static information storage and retrieval

Addressing

Plural blocks or banks

365236, 36523003, 36523006, G11C 800

Patent

active

060440325

ABSTRACT:
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. A unique addressing circuit controlled by an internal clock generates addresses for each plane from one external address. The generated addresses allow both planes to be accessed simultaneously. Thus, two sets of data from two independent planes of memory are simultaneously accessed in one system clock cycle.

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