Addressing of operands within a segment utilizing segment descri

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G06F 932, G06F 936

Patent

active

043853528

ABSTRACT:
A data processing system includes apparatus for addressing operands within a segment utilizing segment descriptors. The apparatus is responsive to instruction words executed by a first of a plurality of processes. An exemplary embodiment includes a first component which stores a segment table containing a plurality of segment descriptors, a plurality of second components, each selectively coupled to the first components and responsive to a selected one of the instruction words, identify the segment table and the location within the segment table and store an offset address within the segment identified by the segment descriptor, a third component is responsive to an address syllable element of an instruction being executed for addressing one of the plurality of second components, a fourth component stores a displacement D from the address syllable, a fifth component is coupled to the second and fourth components for adding the displacement D to the offset whereby an SRA is developed (a segment relative address), a sixth component stores an index for addressing the next sequential word following the currently addressed word and adds the index to the displacement D and to the offset, a seventh component generates an absolute address of an operand contained within the segment and is coupled to the first and fifth components for adding the segment relative address SRA to the base address of the segment descriptor associated with the segment, and an eighth component is coupled to the sixth component for incrementing the absolute address location of the operand to the next word following the currently addressed word.

REFERENCES:
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patent: 4025901 (1977-05-01), Bachman et al.
Microprogramming, Principles and Practices, Husson, 1970, Prentice-Hall, Inc., Englewood Cliffs, N.J., pp. 1-21.

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