Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
1999-12-29
2002-08-06
Brier, Jeffery (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S552000, C345S561000, C345S563000
Reexamination Certificate
active
06429873
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to texture maps in graphics processing. More particularly, it pertains to an addressing scheme for locating texture maps.
2. Description of the Related Art
Modern three dimensional (3D) graphics processors use a number of techniques to speed up graphics processing. One of these techniques is the use of texture maps. When an object is to be depicted in a displayed image, the size of the object in the display will decrease as the perceived distance of the object from the viewer increases. (Note: the word ‘object’, as used herein, applies to any displayable image in a portion of the screen, whether it includes one or more viewable entities, a portion of one viewable entity, a portion of a viewable surface, etc.) It is possible to construct each object from scratch at the proper size whenever the object is to be displayed, but it is much more efficient to construct the object ahead of time and store it for quick retrieval whenever the object is to be displayed. Since the object may be shown in various sizes, several different sizes of the object are constructed and stored for later retrieval. Starting with the largest version, each of these versions is a progressively lower resolution pre-filtered representation of the previous one. A group of these differently-sized versions of the same object is collectively referred to as a mip-map. Each differently-sized version, which are referred to herein as maps, is associated with a certain Level of Detail (LOD) parameter. The most common maps progress in powers of 2, so that each successive map (LOD
0
, LOD
1
, LOD
2
, etc.) has half the horizontal and vertical dimensions as the previous map.
In conventional implementations, the various maps of a single mip-map are spread throughout storage memory in such a way that the starting point for each map (the starting memory address where each map resides) is not related to the starting point of any other associated map. Because of this, a graphic engine that generates memory accesses for different LODs will have to internally store the starting address for every map. In addition, modern graphics engines tend to have several mip-maps active at one time, each one with its own set of maps, which multiplies the number of addresses that must be stored and the amount of memory that must be devoted to this function.
SUMMARY OF THE INVENTION
An embodiment of the invention includes a subtractor circuit having first and second subtractor inputs and a first subtractor output to generate a first difference signal. It also includes a first mask circuit having a first mask input coupled to the first subtractor input and a first mask output to generate a first thermal mask, and further includes a second mask circuit having a second mask input coupled to the first subtractor output and a second mask output to generate an inverted second thermal mask. It also includes a combinatorial logic circuit to perform a logic operation on the first and inverted second thermal masks, with the combinatorial logic circuit having a first logic input coupled to the first mask output, a second logic input coupled to the second mask output, and a first logic output.
REFERENCES:
patent: 5706481 (1998-01-01), Hannah et al.
patent: 5953015 (1999-09-01), Choi
patent: 5963220 (1999-10-01), Lee et al.
Cook Val G.
Doyle Peter L.
Kacevas Nicolas I.
Blakely , Sokoloff, Taylor & Zafman LLP
Brier Jeffery
Fouladi Faranak
Intel Corporation
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