Addressing modes for a dynamic single bit per cell to multiple b

Details Addressing modes for a dynamic single bit per cell to multiple b Addressing modes for a dynamic single bit per cell to multiple b

1995-10-10

1996-11-12

Nelms, David C.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36518503, 36518533, 36523008, G11C 1156, G11C 1134

Patent

active

055748791

ABSTRACT:
A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory space and the physical addresses when operating in the standard cell mode.

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