Addressing means for random access memory system

Details Addressing means for random access memory system Addressing means for random access memory system

1979-08-13

1982-03-02

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 936

Patent

active

043181759

ABSTRACT:
A method and apparatus for addressing memory locations in a random access memory system having m address lines and 2 Exp(m+n) address locations. The random access memory system is divided into a plurality of 2 Exp(n) memory modules, each memory module having 2 Exp(m) memory locations. Each of the memory modules is divided into 2 Exp(n) groups of 2 Exp(m-n) memory locations. In a specific embodiment in which m=15 and n=4, each memory module contains 2 Exp(15) or 32,768 address locations, and the sixteen memory modules together contain 524,288 address locations. Each memory module is divided into 2 Exp(4) or sixteen groups of memory locations. The first or most significant 4 bits of a 15 bit address word are used to address one of the sixteen groups of memory locations and also to address a particular memory module containing the addressed group. This is accomplished in an address translation logic unit which is preprogrammed so that the first four bits enable a particular memory module containing the addressed group of memory locations. Thus, the first four bits actually are used to address 256 possible groups of memory locations (sixteen groups in each of sixteen memory modules). By appropriately programming the address translation logic unit, sixteen groups of discontinuous memory spaces in the sixteen memory modules can be directly accessed by a computer central processing unit (CPU).

REFERENCES:
patent: 4005389 (1977-01-01), Penzel
patent: 4024509 (1977-05-01), Elmer
patent: 4037215 (1977-07-01), Birney et al.
patent: 4048624 (1977-09-01), Cochran et al.
patent: 4118773 (1978-10-01), Raguin et al.

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