Addressing for large dynamic RAM

Details Addressing for large dynamic RAM Addressing for large dynamic RAM

1989-12-04

1991-06-25

Fears, Terrell W.

Static information storage and retrieval

Addressing

Multiplexing

36518902, G11C 1300

Patent

active

050273299

ABSTRACT:
A DRAM semiconductor memory chip comprised of a matrix of rows and columns having a bit storage cell at each location, means for receiving row and column address bits in multiplexed form on a single address bus, the multiplexing arrangement being such that the number of column address bits exceeds the number of row address bits, whereby a system using the DRAM memory chip has access to an enlarged page size.

REFERENCES:
patent: 4754433 (1988-06-01), Chin et al
patent: 4845677 (1989-07-01), Chappell et al.

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