Addressing data within dynamic random access memory

Details Addressing data within dynamic random access memory Addressing data within dynamic random access memory

2006-11-28

2006-11-28

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060, C365S230080, C711S200000, C711S220000

Reexamination Certificate

active

07142479

ABSTRACT:
A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides—dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

REFERENCES:
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5428770 (1995-06-01), Garner
patent: 5499385 (1996-03-01), Farmwald et al.
patent: 5517459 (1996-05-01), Ooishi
patent: 5657288 (1997-08-01), Dent
patent: 5815510 (1998-09-01), Jones et al.
patent: 6292403 (2001-09-01), Pancholy et al.

Affiliated with

Also associated with

Rating

Addressing data within dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Addressing data within dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Addressing data within dynamic random access memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3673883