Patent
1991-12-19
1994-10-18
Shaw, Dale M.
395575, G06F 1502
Patent
active
053576152
ABSTRACT:
A circuit and processing logic is used to test, configure, and control the operation of computer system resource addressing control signals. The programmable circuit of the present invention determines when, in an I/O access cycle, the resource addressing control (IOCHRDY) signal should be activated by an I/O mapped system resource. The present invention includes lost circuitry for determining whether a particular system resource operates best in a late IOCHRDY mode or an early IOCHRDY mode. The test logic will force the IOCHRDY signal to remain active for an extended period of time. By extending the deactivation time of the IOCHRDY signal far beyond the time at which the deactivation would normally occur, the responsiveness of a command strobe (IORD/IOWR) may be tested. If the deactivation of the command strobe IORD/IOWR follows the extended deactivation time of the IOCHRDY signal, the command strobe (IORD/IOWR) is properly responsive to the IOCHRDY signal and proper operation of the I/O access control logic is verified. If, however, the extended activation of the IOCHRDY signal causes the command strobe (IORD/IOWR) to deactivate prior to the deactivation of the IOCHRDY signal, a nonresponsive command strobe (IORD/IOWR) signal is present and thus a failure condition is detected. A processor-readable bit in a control register indicates a successful or unsuccessful IOCHRDY test condition.
REFERENCES:
patent: 4023142 (1977-05-01), Woessner
patent: 5029166 (1991-07-01), Jarwala et al.
patent: 5144627 (1992-09-01), Horie et al.
patent: 5157781 (1992-10-01), Harwood et al.
patent: 5157782 (1992-10-01), Tuttle et al.
Cedros Craig D.
Peek Greg A.
Intel Corporation
Meky Moustafa M.
Shaw Dale M.
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