Static information storage and retrieval – Addressing – Sequential
Patent
1985-01-30
1987-06-30
Fears, Terrell W.
Static information storage and retrieval
Addressing
Sequential
365 45, 365230, G11C 1300
Patent
active
046775943
ABSTRACT:
Addressing circuit for a matrix display having shift registers formed by static memories and process for addressing with such a circuit.
For a display with p columns, the circuit comprises p register points formed by static memories (M.sub.i), a first series of switches (C.sub.1) placed in front of the register points M.sub.k-1, k being an even number between 1 and p, a second series of switches (C.sub.2) placed in front of the register points M.sub.k and a transfer clock (13) producing a first signal (.phi..sub.1) controlling the first series of switches, in order to ensure the loading of a "1" signal into the register point (M.sub.1) and the transfer of the content of register point M.sub.k to register point M.sub.k+1, and a second signal (.phi..sub.2) controlling the second series of switches for ensuring the transfer of the content of register point M.sub.k-1 to register point M.sub.k.
REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4393482 (1983-07-01), Yamada
Flache Fernseh-Bildschirme by A. Fischer, Nachrichtentechnische Zeitschrift NTZ, vol. 33, No. 2.
Handbuch der Digitalen Schaltungen, by E. A. Zuiderveen
Bisotto Sylvette
Blanc Jean-Philippe
Bodin Bernard
Poujois Robert
Commissariat a l''Energie Atomique
Fears Terrell W.
Meller Michael N.
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