Addresses generation for interleavers in turbo encoders and...

Coded data generation or conversion – Digital code to digital code converters – To or from interleaved format

Reexamination Certificate

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C341S050000

Reexamination Certificate

active

10538898

ABSTRACT:
An arrangement for generating addresses for interleaving/de-interleaving sequences (X1, X2, X3, . . . , XK) including a given number (K) of items, wherein each value for said given number (K) identifies a corresponding set of interleaving parameters (R, C, p, v). The arrangement has at least one memory unit wherein a plurality of records are stored, each record being indicative of a respective set of parameters (R, C, p, v) corresponding to at least one value for said given number (K). Sets of interleaving parameters (R, C, p, v) are thus available in the memory unit to be promptly and directly retrieved for all possible values of said given number of items (K). A preferred use is in turbo encoders/decoders for advanced telecommunications applications such as UMTS.

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Gutab, A., “A Modulo Multiplication Hardware Design,” Oregon State University-Electrical & Computer Engineering Department-ECE 575 Project Report, pp. 1-8 (2000), no month.
Specification 3GPP TS 25.212, V3.5.0, (Dec. 2000), 2 pages, Release 1999, no month.
Masera et al., “Low-Cost IP-Blocks for UMTS Turbo Decoders”, Proceedings of ESSCIRC, 4 pages, (Sep. 2001).
Crozier et al., “High-Performance Low-Memory Interleaver Banks for Turbo-Codes”, Proceedings of IEEE 54th, vol. 1, pp. 2394-2398, (Oct. 7, 2001).

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