Addressable transceiver module

Details Addressable transceiver module Addressable transceiver module

2001-06-01

2003-04-29

Healy, Brian (Department: 2874)

Optical waveguides

With disengagable mechanical connector

Optical fiber to a nonfiber optical device connector

C385S092000, C359S199200, C359S199200, C439S076100

Reexamination Certificate

active

06554492

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to removable serial transceiver modules, and more particularly, to an addressable gigabit interface converter (GBIC) having a distinctive address.
BACKGROUND OF THE INVENTION
Removable serial transceiver modules, such as GBICs, are designed to provide gigabaud capability for Fibre Channel (FC) and other protocols that use similar optical fiber links. In general terms, the GBIC provides an interface between a serial duplex optical interface, such as an FC port, and a serial duplex electrical device such as a serializer/deserializer (SERDES). The electrical connector specified for a GBIC is a 20-pin Single Connector Attachment (SCA-20), which is a male ribbon style connector. GBICs are designed to be “hot-pluggable,” meaning the host receptacle can remain powered on during installation of a GBIC. More detailed information of the GBIC is provided in the “SFF Committee Proposed Specification for GBIC (Gigabit Interface Converter),” Revision 5.5, dated Sep. 27, 2000, which is hereby incorporated by reference.
A host system generally includes one or more host receptacles, usually mounted to a host printed circuit board (PCB). Once a GBIC is installed into a host receptacle, the host system identifies the specific type of GBIC by reading the module definition of the GBIC. The module definition of a GBIC is indicated by three (3) module definition pins, which are pins #
4
, #
5
, and #
6
within the electrical connector of the GBIC. These three pins enable eight (8) different binary module definitions to be identified. For example, module definition “0” indicates that no GBIC is present, module definition “1” indicates a copper style GBIC with an active inter-enclosure connection, module definition “3” indicates an optical 1300 nanometer GBIC, etc.
Module definition
4
is somewhat unique. GBIC module definition
4
specifies a serial definition protocol. If the host system detects module definition
4
, the serial protocol may then be activated. When the serial protocol is activated, the serial clock signal (SCL) is generated by a host controller, which is contained within the host system. A GBIC having a module
4
definition provides access to sophisticated identification information that describes the GBIC's capabilities, standard interfaces, manufacturer, and other information.
According to the GBIC specification, the serial interface uses a modified two-wire I
2
C™ protocol (trademarked by Phillips Corporation) to access the information stored in an E
2
PROM. The protocol requires the master I
2
C™ bus host controller to send a device address, which is one byte (8 bits) long, followed by a word address. The word address is also one byte long and is used to access a specific address in the E
2
PROM. The size of the word address (one byte) determines the maximum number of directly addressable words in the memory as 2
8
=256. Each memory address contains one byte of information, so the maximum capacity is 2K bits. If the E
2
PROM has only one-kilobit capacity, the Most Significant Bit (MSB) of the address word is disregarded.
The device address word is eight bits long. The first four MSBs contain a mandatory one zero sequence followed by three bits for device/page addressing. The eighth bit of the word determines the type of operation as a Read (one) or Write (zero).
The three device/page addressing bits of the Device Address Word allow up to eight 1K/2K E
2
PROMs to be connected simultaneously to the I
2
C™ bus or fewer 4K/8K/16K E
2
PROMs. The 1K/2K E
2
PROMs have three hardwire pins, which establish its address. Each of these pins is usually hardwired to Ground or Power, or connected to hardware, which provides the address. Every time a device address word is sent, the three address pins are being compared to the information on the corresponding input address pins. After comparing the device address, the E
2
PROM will output a zero. If a comparison is not made, the chip will remain in a standby state.
The 4K/8K/16K E
2
PROMs use some or all three address/page bits in order to access different pages in its memory. Thus, there can be no more than four 4K, or two 8K, or one 16K E
2
PROMs connected to a single bus.
Pursuant to the GBIC Specification, the address select pins for the serial CMOS E
2
PROM are set to zero. As discussed above, the zero address is achieved by internally hard-wiring all the address pins of the CMOS E
2
PROM to ground (V
IL
low level).
While the type of GBIC connected to a specific host receptacle can be readily identified by the host system, multiple GBICs connected to the same host system cannot be readily distinguished from each other. As previously stated, all GBICs are specified to have an address of zero by grounding the address pins of the serial CMOS E
2
PROM. Since all GBICs have an address of zero, a host system cannot distinguish between multiple GBICs connected to the same I
2
C™ serial communication bus. The conventional technique for a host system to distinguish between multiple GBICs is to provide separate wiring for each GBIC. Conventional GBICs cannot be distinguished on a common I
2
C™ serial communication bus because multiple conventional GBICs would have the same address.
If GBICs could be addressable with unique addresses, then a single host system could accommodate multiple GBICs. Furthermore, multiple GBICs could share a common serial communication bus. Such a common bus could accommodate multiple GBICs that could be accessed by a single host controller. Moreover, using a common bus to access multiple GBICs reduces hardware by eliminating individual wiring necessary to access conventional, non-distinct GBICs. Such a reduction eliminates up to 14 I/O pins on an 8-port media access controller chip by consolidating eight 2-wire interfaces into a single 2-wire serial communication bus.
Accordingly, there is a need for an addressable GBIC whose address can be varied to provide a unique address.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention is to provide a transceiver module, such as a GBIC, having a variable, distinct address that is set by a host receptacle.
A second object of the present invention is to provide an addressable GBIC that can be inputted into a conventional host receptacle designed to receive a conventional GBIC.
A further object of the present invention is to enable a host receptacle to accommodate an addressable GBIC according to the present invention with only minimal modifications.
In that regard, the present invention provides an optoelectronic transceiver module, comprising a housing having a first opening at a first end and a second opening at a second end; a printed circuit board mounted within the housing; an electrical connector on the printed circuit board at the first end of the optoelectronic transceiver module, the electrical connector having an insulative mating surface within the first opening and including a first side with electrical contacts in an area oriented substantially parallel to the first side of the insulative mating surface, wherein the electrical contacts slidingly engage a circuit card connector of a host receptacle in order to quickly install and remove the optoelectronic transceiver module from within the circuit card connector; an optical assembly on the printed circuit board at the second end of the optoelectronic transceiver module, the optical assembly including a transmitting optical subassembly and a receiving optical subassembly, the second opening allowing the optical assembly to communicate outside of the housing in order for the optical assembly to be coupled with a duplex fiber optic plug providing for bi-directional data transmission over an optical data link; and a data storage module within the housing having a configurable address corresponding to the address of the optoelectronic transceiver module and address contacts electrically connected to at least some of the electrical contacts of the electrical connector, thereby enabling a host system to communicate with

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