Addressable serial test system

Details Addressable serial test system Addressable serial test system

1995-05-15

1999-02-23

Decady, Albert

Excavating

G01K 3128

Patent

active

058751971

ABSTRACT:
An addressable serial test system employs a serial register with parallel outputs. Data is clocked into the serial register via a shift clock signal. A decoder is connected to a portion of the shift register's outputs and provides a selection signal dependent on the data clocked into the serial register. A system clock generates a system clock signal. A storage element includes a clock input coupled to the system clock signal, a data input, an output, a load input coupled to the selection signal, and a test data input coupled to another portion of the shift register's outputs. The storage element's output is alternately forced to a state indicative of the test data input by the selection signal and forced to a state indicative of the data input by the system clock. Structure is included to configure the serial register to read the contents of the storage element.

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Thomas W. Williams, Kenneth P. Parker, "Design for Testability--A Survey," Proceedings of the IEEE, vol. 71, No. 1, Jan. 1983.

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