Addressable output buffer architecture

Details Addressable output buffer architecture Addressable output buffer architecture

1998-09-30

2002-06-18

Chauhan, Ulka J. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S558000, C345S536000

Reexamination Certificate

active

06407740

ABSTRACT:

CROSS REFERENCE TO ATTACHED COMPACT DISK APPENDIX
A Compact Disk Appendix, of which two identical copies are attached hereto, includes Appendix 1 and Appendix 2. This Compact Disk Appendix forms a part of the present disclosure and is incorporated herein by reference. The Compact Disk Appendix contains the following files: Append~1.txt, 26 KB, Nov. 29, 2001, and Append~2.txt, 45 KB, Nov. 29, 2000.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
The present invention relates to data processing, and more particularly to processing of computer graphics geometry data.
Constructing images from computer graphics geometry data (sometimes called computer graphics data) involves the pictorial synthesis of real or imaginary objects from their computer based models. Such image construction may require a large number of computations. The computations for each object may have to be frequently repeated if objects move or lighting parameters change. Therefore, it is desirable to increase the speed of the computer graphics geometry data processing.
SUMMARY
The present invention provides in some embodiments methods and apparatus for high speed processing of computer graphics geometry data. The incoming geometry data are buffered in one or more buffers. The data are written to the buffers in an order which is not necessarily the order in which a processor or processors need the data for fast processing. The data are provided to the processors in the order needed for fast processing.
In some embodiments, the geometry data processing has a critical path, and the data for the critical path are provided to the processors early, when the processors need such data. For example, in some embodiments, the lighting computations take more time than the position computations, and hence the lighting computations form a critical path. The position computations are performed by using processor resources not used for the lighting computations.
For instance, in some embodiments, the processor instruction execution is pipelined. The critical path instructions are spread out so as to avoid pipeline stalls that could be caused by data dependencies between instructions. More particularly, if for example an instruction I
1
uses results of a previous instruction, and the previous instruction is still in the pipeline and its results have not become available, the instruction I
1
may have to be stalled. In some embodiments, the critical path instructions are spread out so as to avoid such stalls or reduce their frequency. When a critical path instruction cannot be started without causing a stall, a non-critical path instruction is started. Thus, non-critical path instructions use instruction execution resources not used by critical path instructions. The geometry data processing therefore becomes faster.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.


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