Addressable high speed counter array

Details Addressable high speed counter array Addressable high speed counter array

1996-07-10

1997-11-11

Olms, Douglas W.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

H04L 1256

Patent

active

056871732

ABSTRACT:
Method and apparatus are disclosed for maintaining operational and statistical information in a high speed network switch for each of a plurality of supported connections. A high speed array is provided which includes a plurality of high speed registers for each of a plurality of connections supported by the switch. Upon receipt of a cell/frame, a connection identifier is generated to identify the connection within the network switch and the connection identifier is stored in an index register. The connection identifier stored within the index is used to select a plurality of registers within the high speed register array of registers pertaining to the specified connection. Information pertaining to each received cell/frame is generated upon receipt of the cell or retrieved from the respective cell header and is employed to generate an operand for each of the plurality of registers addressed by the connection identifier. Operands may allow for the clearing, setting, incrementing, decrementing or maintenance of the register contents. Each of the plurality of registers identified by the connection identifier is updated in parallel within the time frame associated with the receipt of a frame/cell.

REFERENCES:
patent: 4849968 (1989-07-01), Turner
patent: 5309432 (1994-05-01), Kanakia
patent: 5548588 (1996-08-01), Ganmukhi et al.
patent: 5557610 (1996-09-01), Calamvokis et al.

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