Addressable delay memory

Details Addressable delay memory Addressable delay memory

1986-06-27

1989-03-07

Buczinski, Stephen C.

Boots, shoes, and leggings

G06F 100

Patent

active

H00006076

ABSTRACT:
An addressable delay memory device which operates as a dual mode device. In he first mode, the addressable delay memory functions as a first in-first out delay memory in which the data is delayed for a predetermined period. In the second mode, the addressable delay memory operates under the control of a remote controller and delays input data for three predetermined periods. The input data is sequentially stored in each of three sections of a dynamic random access memory means with the three delays being determined by the time required to fill each of the three sections. The delayed data from each of the three sections is coupled to a static random access memory means. The remote controller may request that the data words from any of the three groups of delayed data be placed on the output of the addressable delay memory device.

REFERENCES:
patent: 4080652 (1978-03-01), Cronshaw et al.
patent: 4249247 (1981-02-01), Patel
patent: 4414664 (1983-11-01), Greenwood
patent: 4451918 (1984-05-01), Gillette

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