Address translator with by-pass circuit and method of operation

Details Address translator with by-pass circuit and method of operation Address translator with by-pass circuit and method of operation

1994-04-04

1996-07-09

Lane, Jack A.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365 49, G06F 1210, G11C 1500

Patent

active

055353517

ABSTRACT:
An address translator (42) with a by-pass circuit (106) translates a received effective address into a real address in a first mode of operation by matching a portion of the effective address and a stored translation tag. The address translator outputs a real address corresponding to the matching translation tag on a plurality of bit lines (BIT LINE). The by-pass circuit connects the input effective address to the bit lines in a second mode of operation. The address translator thereby eliminates the need for a subsequent two-to-one multiplexer.

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Furht et al., `A Survey of Microprocessor Architectures for Memory Management`, IEEE, Mar., Computer 1987, pp. 48-67.
Baliga, Designing with the Virtual Memory 80386, Baliga; Intel Corporation, pp. 1-5.

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