Address translation method and apparatus therefor

Details Address translation method and apparatus therefor Address translation method and apparatus therefor

1988-11-09

1991-02-12

Eng, David Y.

Boots, shoes, and leggings

3642549, 3642551, 3642557, G06Z 1208, G06Z 1210

Patent

active

049929364

ABSTRACT:
In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address translation sizes is prepared; the logical address designated by the program is fetched; an entry of an address translation table whose address translation size is larger than those of the other address translation tables among the plurality of address translation sizes is first identified based on the fetched logical address; a first information on an address translation size validity included in the first indentified entry is checked; address translation in units of translation size of the address translation table including the first identified entry is performed when the first information indicates valid; when the first information indicates invalid, an entry of an address translation table whose address translation size is next smaller than that of the address translation table including the first identified entry is second identified, based on the top address of the address translation table including the second identified entry and based on the fetched logical address; and address translation is further performed returning back to the above-mentioned step where the first information on the address translation size included in the first identified entry is checked.

REFERENCES:
patent: 3979729 (1976-09-01), Eaton et al.
patent: 4079453 (1978-03-01), Dahl
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4727485 (1988-02-01), Keshlear et al.
"Hitac Supercomputer S-820 Functional Description", Jun. 1987.
"Hitac S-820 Processor Manual", May 1988.

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