Address translation managing system with translation pair purgin

Details Address translation managing system with translation pair purgin Address translation managing system with translation pair purgin

1976-03-22

1978-01-10

Thomas, James D.

Boots, shoes, and leggings

G06F 920, G06F 1300

Patent

active

040683036

ABSTRACT:
In a data processing system employing a virtual storage system, a plurality of address translation pairs each consisting of a logical address in a virtual storage space and a real address in a real storage space, are registered in a buffer storage device to swiftly translate a logical address into the corresponding real address. According to this invention, in the case of purging a virtual space out of multiple virtual spaces only the address translation pairs corresponding to the virtual space are purged so that the processing performance of the data processing system can be improved.

REFERENCES:
patent: 3588839 (1971-06-01), Belady
patent: 3902163 (1975-08-01), Amdahl

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