Patent
1994-08-02
1996-07-23
Lane, Jack A.
395486, 395460, G06F 1212
Patent
active
055398928
ABSTRACT:
A data processor (10) has a translation lookaside buffer, a "TLB," (56) for translating internal effective addresses into external real addresses. A user programmable bit in a special purpose register (68) controls which TLB entry in a group of entries will be replaced after an unsuccessful translation. Normally, the data processor uses a hardware controlled algorithm to select an entry for replacement. However, the user can overwrite the value in the special purpose register to force a certain replacement scheme. The user can thereby protect certain important translation mappings or deterministically test the TLB after manufacture.
REFERENCES:
patent: 4631660 (1986-12-01), Woffinden et al.
patent: 5276848 (1994-01-01), Gallagher et al.
Reininger Russell
Slaton Jeff
Chastain Lee E.
Lane Jack A.
Motorola Inc.
Verbrugge Kevin
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