Address translation in FFT numerical data processor

Details Address translation in FFT numerical data processor Address translation in FFT numerical data processor

1991-05-28

1993-06-29

Malzahn, David H.

Boots, shoes, and leggings

G06F 15332

Patent

active

052240630

ABSTRACT:
A numerical data processor includes first and second registers for receiving and holding input data from a memory, respectively, and a multiplier receiving the input data held in the first and second registers for multiplying the input data held in the first register by the input data held in the second register. A translated address generation circuit is coupled to the memory for generating a translation address of two bits for translation of an address of the input data to be supplied to the register, and an addition/integration circuit receives an output of the multiplier for performing an addition/integration of the output of the multiplier. A controller operates to control the memory, the registers and the translated address generation circuit in a programmed manner so that a Fourier transform, is executed for a given data.

REFERENCES:
patent: 3584782 (1971-06-01), Bergland
patent: 3731284 (1973-05-01), Thies
patent: 3777131 (1973-12-01), Llewellyn
patent: 4393457 (1983-07-01), New
patent: 4477878 (1984-10-01), Cope
patent: 4630229 (1986-12-01), D'Hondt
patent: 4689762 (1987-08-01), Thibodeau, Jr.

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