Address translation device with an address translation buffer lo

Details Address translation device with an address translation buffer lo Address translation device with an address translation buffer lo

1990-10-30

1993-08-03

Dixon, Joseph L.

Boots, shoes, and leggings

395425, 364DIG1, 364DIG2, G06F 1200

Patent

active

052337006

ABSTRACT:
In an address translation device (11) used in combination with a main memory (12) in translating an input virtual address into an output real address, an address translation buffer (15) is for memorizing not only a plurality of buffer virtual addresses (BVA) and a plurality of buffer real addresses (BRA) corresponding to respective buffer virtual addresses but also buffer presence bits (BP) corresponding to respective buffer real addresses to indicate presence or absence of a datum of a memory real address in the main memory in correspondence to each of the buffer real addresses. A comparison control circuit (17) compares the input virtual address with a particular one of the buffer virtual addresses, that corresponds to the input virtual address to make the address translation buffer produce, as the output real address, a particular one of the buffer real addresses, which corresponds to the particular buffer virtual address when the input virtual address coincides with the particular buffer virtual address.

REFERENCES:
patent: 4084225 (1978-04-01), Anderson et al.
patent: 4177510 (1979-12-01), Appell et al.
patent: 4285040 (1981-08-01), Carlson et al.
patent: 4520441 (1985-05-01), Bandoh et al.
patent: 4641277 (1987-02-01), Yata et al.
patent: 4794524 (1988-12-01), Carberry et al.
Patent Abstracts of Japan, vol. 7, No. 15 (P-169), Jan. 21, 1983, [JP-A-57 169 984].
"IBM Enterprise Systems Architecture/370 Principles of Operation", 1989, pp. 3-47, IBM Publication No SA22-7200-0.

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