Address translation device capable of obtaining a real address f

Details Address translation device capable of obtaining a real address f Address translation device capable of obtaining a real address f

1992-05-29

1995-01-31

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, 364243, 3642434, 36424341, 36424345, 3642472, 3642563, 3642564, G06F 1208, G06F 1210

Patent

active

053865308

ABSTRACT:
In an address translation device having a main address translation unit (20) with a main access time that translates an input virtual address into a main real address, a subsidiary address translation unit (30) is connected to the main address translation unit (20). The subsidiary address translation unit (30) has a subsidiary access time shorter than the main access time and translates the input virtual address into a subsidiary real address. Connected to the main address translation unit (20) and the subsidiary address translation unit (30), an output address production unit (40) selectively produces one of the main real address and the subsidiary real address as an output real address. The subsidiary address translation unit (30) has an access/real address register (31) holding a buffer access address of the input virtual address and the main real address as a held access address and a held real address, respectively.

REFERENCES:
patent: 3761881 (1973-09-01), Anderson et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5226133 (1993-07-01), Taylor et al.
patent: 5305444 (1994-04-01), Becker et al.
IBM Technical Disclosure Bulletin, Ngai et al. "Two-Level DLAT Hierarchy" vol. 24, pp. 4714-4715, (1982).
A. Khan, "CMOS and ECL Implementation Of MIPS RISC Architecture," Microprocessors and Microsystems, vol. 14:367-375, (1990).

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