Address translation circuit including two translation buffers

Details Address translation circuit including two translation buffers Address translation circuit including two translation buffers

1987-03-23

1989-07-18

Chan, Eddie P.

Boots, shoes, and leggings

G06F 1202

Patent

active

048498769

ABSTRACT:
An address translation circuit for translating a logical address into a physical address in a computer system using a virtual storage method includes two high-speed buffers (TLB's) for an instruction and an operand, respectively. One of the buffers is selected for use at the time of a memory access depending on a signal supplied from a processing unit to indicate whether the memory access is related to an instruction cycle or an operant cycle. This configuration enables a high-speed address translation without lowering the TLB hit rate and without increasing the amount of the hardware components.

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