Address translation buffer for data processing system emulation

Details Address translation buffer for data processing system emulation Address translation buffer for data processing system emulation

1997-09-22

1999-09-14

Teska, Kevin J.

G06F 9455

Patent

active

059535202

ABSTRACT:
A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in memory. The series includes a guest memory access instruction that indicates a guest logical address in guest address space. For each guest instruction in the series, a semantic routine of native instructions from the native instruction set is stored in memory. The semantic routines, which utilize native addresses in native address space, can be executed in order to emulate the guest instructions. In response to receipt of the guest memory access instruction for emulation, the guest logical address is translated into a guest real address, which is thereafter translated into a native physical address. A semantic routine that emulates the guest memory access instruction is then executed utilizing the native physical address.

REFERENCES:
patent: 5339417 (1994-08-01), Connell et al.
patent: 5574873 (1996-11-01), Davidian
patent: 5742802 (1998-04-01), Harter et al.
patent: 5790825 (1995-11-01), Traut

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