Address translation buffer control system

Details Address translation buffer control system Address translation buffer control system

1983-06-30

1986-08-05

Thomas, James D.

Boots, shoes, and leggings

G06F 1210, G06F 1214

Patent

active

046046887

ABSTRACT:
A computer virtual memory system having a translation lookaside buffer (TLB) in which the result of a dynamic address translation system is stored when in a normal mode or when a non-privileged instruction is executed, but the result is not stored when in a privileged mode or when a privileged instruction is executed, such as a storage key operation. The storage does not occur even though the effective address of the privileged instruction is translated into a physical address.

REFERENCES:
patent: 4038645 (1977-07-01), Birney
patent: 4096573 (1978-06-01), Heller
patent: 4241401 (1980-12-01), De Ward
patent: 4410941 (1983-10-01), Barrow
patent: 4430705 (1984-02-01), Cannavino
patent: 4439830 (1984-03-01), Chueh
patent: 4481573 (1984-11-01), Fukunaga
patent: 4500952 (1985-02-01), Heller
Drimak et al., "Directory Look-Aside Table Controls", IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 1266-1267.
Heald, "Address Translation Bypass", IBM Technical Disclosure Bulletin, vol. 18, No. 10, Mar. 1976, pp. 3373-3375.
IBM System/370 Principles of Operation, Fourth Edition (Sep. 1974), pp. 38-39, 105, 107-108 and 110.

Affiliated with

Also associated with

Rating

Address translation buffer control system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address translation buffer control system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address translation buffer control system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-972058