Address translation buffer

Details Address translation buffer Address translation buffer

1983-07-14

1985-08-27

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1300

Patent

active

045382417

ABSTRACT:
An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.

REFERENCES:
patent: 3806883 (1974-04-01), Weisbecker
patent: 4410941 (1983-10-01), Barrow et al.
patent: 4453230 (1984-06-01), Mizoguchi et al.

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