Address translation apparatus

Details Address translation apparatus Address translation apparatus

1978-07-17

1980-08-19

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 920

Patent

active

042187435

ABSTRACT:
Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated. If the two compare then the real address which had been used to access the page directory is entered into a register so as to be available as a real main storage address. In actuality it is only a partial real main storage address and is concantenated with a byte identifier portion of the main storage address which requires no translation and which was a part of the original I/O real address for main storage.

REFERENCES:
patent: 3781808 (1973-12-01), Ahearn et al.
patent: 3854126 (1974-12-01), Gray et al.
patent: 3902164 (1975-08-01), Kelley
patent: 3938096 (1976-02-01), Brown
patent: 4057848 (1977-11-01), Hayashi
"Scatter Storage Technique," Robert Morris, Communications of the ACM, vol. II, No. 1, Jan. 1968, pp. 38-44.

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