Address translating apparatus for translating virtual address in

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Details

395425, 3642449, 3642551, 3642581, 3642592, 364DIG1, G06F 1208

Patent

active

053496507

ABSTRACT:
An address translating circuit is disclosed for translating a virtual address signal generated from an external CPU into a real address signal applicable to the dual-port random access memory (DPRAM) in the microcomputer. This address translating circuit includes an offset register, an enabling signal generating circuit, and a subtractor provided in the microcomputer. The offset data obtained based upon the difference between an address map handled by the external CPU and an address map handled by the internal CPU is set in the offset register. The enabling signal generating circuit is responsive to the more significant bits of the virtual address signal and the offset data to generate an enabling signal. The subtractor is responsive to the intermediate bits of the virtual address signal and the offset data to generate a translated address signal. Since the address translation is performed by circuit operation without depending on the processing of the external CPU, the burden on the external CPU is reduced

REFERENCES:
patent: 4829420 (1989-05-01), Stahle
patent: 5146607 (1992-09-01), Sood et al.
patent: 5175536 (1992-12-01), Aschliman et al.

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