Address-translatable graphic processor, data processor and drawi

Details Address-translatable graphic processor, data processor and drawi Address-translatable graphic processor, data processor and drawi

1994-09-06

1996-04-09

Powell, Mark R.

395164, 395166, 395412, G06F 1516

Patent

active

055070264

ABSTRACT:
In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address so as to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit and graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.

REFERENCES:
patent: 4737909 (1988-04-01), Harada
patent: 4791580 (1988-12-01), Sherrill et al.
patent: 4860192 (1989-08-01), Sachs et al.
patent: 5369744 (1994-11-01), Fukushima et al.
Wescon Technical Papers, Oct. 1984, "Graphic Display Processor to Integrate Drawing Algorithm and Display Controls" by Katsura et al.

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