Address-translatable graphic processor, data processor and drawi

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395163, 395400, 395325, 3642302, 3642412, 3642808, 36492792, 36493541, G06F 1520

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active

053697448

ABSTRACT:
In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them. Furthermore, the graphic processing system includes a drawing processing unit connected to the system bus interface, for translating the virtual address into the physical address to access the main memory and to process the data, a bus arbitrator for performing arbitration between demands for using the interface given from the central processing unit add graphic processor, and a suspend circuit for asserting a signal requesting that the interface is released to the central processing unit.

REFERENCES:
patent: 4376296 (1983-03-01), Anderson et al.
patent: 4737909 (1988-04-01), Harada
patent: 4791580 (1988-12-01), Sherrill et al.
patent: 4860192 (1989-08-01), Sachs et al.
patent: 4862150 (1989-08-01), Katsure et al.
patent: 4967374 (1990-10-01), Nomura et al.
"Graphic Display Processor to Integrate Drawing Algorithms and Display Controls" by Katsura et al, 8080 Wescon Technical Papers Oct. 30-Nov. 2, 1984, LA, USA.

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