Address transition detector in semiconductor memories

Details Address transition detector in semiconductor memories Address transition detector in semiconductor memories

1999-10-06

2001-04-03

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100

Reexamination Certificate

active

06212128

ABSTRACT:

SPECIFICATION
1. Field of the Invention
The present invention relates to an address transition detector in semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to give out output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit including bistable memory circuits for storing the values of the address transition signals at each logical status changement of the address signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals.
2. Background of the Invention
Address transition detectors known as ATD (Address Transition Detection) are used in semiconductor memories for providing the initial pulse for those memories, which even if not driven by an external clock signal, i.e. asynchronous, can operate as if they were driven through an internal clock signal, i.e. as if they were synchronous.
ATD circuits generate a single pulse when one or more of their inputs—which may be represented by address signals or any selection signals—change their logic status. A pulse acts like an original clock signal for subsequent clock signals controlling timings of various internal operations. Said internal operations, mostly related to read cycles, include for instance bitlines precharge and equalization operations, as well as automatic switch-off functions of the memory circuit.
Since an ATD circuit driving a read cycle is a circuit sensing any transition occurring within the addressing lines, it follows that an ATD circuit should have high transition sensitiveness, a fast response to transitions, capture capability for any kind of transition related to the addressing lines.
ATD circuits, due to their nature of original clock signals, start read cycles and operate resetting of read cycles, which were possibly previously started by the ATD circuits themselves.
This means that a new read cycle cannot be started if a previous read cycle has not been finished; in fact, each read cycle is suddenly interrupted if any kind of transition has occurred for any reason on the address lines and a pulse is generated as a result by the ATD circuit Therefore, any interference of the address lines, such as a transition of output buffers, or disturbances due to capacitive couplings between lines, may either interrupt or start read cycles. Additionally, said disturbances may also tale an oscillatory nature.
As a result of said peculiar operation of ATD circuits, each read request should be regarded as a sum of serial events, which starting from the stimulus of an address lines transition will produce an entire read cycle.
For this reason, early ATD circuits used to include a monostable circuit, obtained through a flip-flop. The monostable circuit just simply sensed each transition at its input, following to which a pulse was emitted. Thus, any interference could produce a pulse and a consequent wrong initialization or blocking of the read cycle.
FIG. 1
shows an address transition detector
1
according to the prior art. Here we have an address signal AD at the input of the address transition detector
1
in a stiffening circuit
2
, where a stiffening circuit means a circuit apt to reduce sensitivity to weak pulses, wherefrom an address transition detector AX and its negate, i.e. a negated address transition detector AN are generated. A monostable circuit
3
is arranged downstream the stiffening circuit
2
for generating a pulse signal GL including a temporary memory circuit
4
for receiving the address transition detector AX. Therefore, the monostable circuit
3
comprises a depletion breaker transistor M
1
on the path of the address transition detector AX and a breaker depletion transistor M
2
on the path of the negated address transition detector AN. The monostable circuit
3
comprises an inverter
5
with an associated pull-up transistor M
3
for recovering the fall due to the threshold of breaker transistors M
1
and M
2
. Transistor input
5
, which also forms the node whereon the pulse signal GL is taken, is connected to both the path related to the address transition signal AX and the path related to the negated address transition signal AN. A second inverter
6
is located downstream, whose output controls a switch transistor M
4
separating the temporary memory circuit
4
from the input of the monostable circuit
3
. The temporary memory circuit
4
consists substantially of a flip-flop obtained by placing an inverter
7
and an inverter
8
in series and taking the inverter output
8
back to the inverter input
7
. Moreover, the inverter output
7
controls the breaker transistor M
1
, whereas the inverter output
8
controls the switch transistor M
2
. A breaker transistor M
5
driven by the output of the inverter
5
is located between the output of the inverter
8
and the input of the inverter
7
. In addition, the inverter
7
also has a pull-up transistor M
6
, similar to the inverter
5
.
Therefore, when for instance the address transition signal AX goes from a low to a high logic level, the pulse signal GL will rise to high level; consequently, there will be a low logic level at the inverter output
5
and a high logic level at the inverter output
7
, which puts the breaker transistor M
5
in conduction. Thus, also at the input of the temporary memory circuit
4
a high logic level will inhibit the breaker transistor M
1
and activate the breaker transistor M
2
, which returns the pulse signal GL to its low level. As a result, the length of the pulse signal GL will depend on the propagation speed of the signal in the monostable circuit
3
. The temporary memory circuit
4
will retain information about the previous address internally.
The stiffening circuit
2
comprises an inverter
9
and an inverter
10
, also configured as a flip-flop or latch, which have a breaker transistor M
7
controlled by a noise signal N on their feedback path. When the signal N is at its high logic level, the feedback path is closed, the address transition signal AX similarly to the address signal AD returned to the input, so that a fake signal will find it more difficult to switch the input of the stiffening circuit i
2
.
However, the use of a stiffening circuit is not a very effective solution, since said circuit cannot be too stiff, i.e. to require an input signal too strong for transition detection, since there is the risk of missing detection of the real address transition. Moreover, since control of pulses duration is poor, some pulses may be “dirty”, making it difficult for the subsequent circuits to sense them.
Finally, said circuit does not allow to adopt a ‘full CMOS’ architecture, so that its use in circuits operating at a low supply voltage, for instance 3.3 Volts, may be difficult.
FIG. 2
shows an address transition detector
21
obtained under ‘full CMOS’ technology. Said address transition detector
21
consists of a transition signals generating circuit
22
and a monostable circuit
23
, which comprises a temporary memory circuit
24
. A driving circuit
29
is provided at the output of the monostable circuit
23
.
The transition signals generating circuit
22
provides a NOR logic gate
30
, whose inputs consist of the address signal AD and a chip enable signal CE. At the output of the logic gate
30
an inverter
28
originates the address transition signal AX and an inverter
31
in series with the inverter
28
generates the negated address transition signal AN.
Address transition signals AX and AN are sent at the input to respective passgate transistors PG
1
and PG
2
, which form the monostable circuit input
23
. The output of said passgate transistors PG
1
and PG
2
produces the pulse signal GL
1
′, which is inverted by the driving circuit
29
and is exited as a pulse signal GL
1
.
Moreover, the signal is picked up at the input of the driving circuit
29
and forwarded in a feedback pat

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