Address transition detector for programmable logic array

Details Address transition detector for programmable logic array Address transition detector for programmable logic array

1989-09-29

1991-10-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307450, 307468, 307471, 307242, 307573, 307576, H03K 1716, G06F 738

Patent

active

050577123

ABSTRACT:
An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the PAL such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.

REFERENCES:
patent: 4831285 (1989-05-01), Gaisen
patent: 4893033 (1990-01-01), Itano et al.
patent: 4906870 (1990-03-01), Gongwen

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