Address transition detection to write state machine interface ci

Details Address transition detection to write state machine interface ci Address transition detection to write state machine interface ci

1992-06-19

1993-09-07

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

365900, 36518908, G11C 800

Patent

active

052435750

ABSTRACT:
A circuit to ensure that a flash memory device with a write state machine ("WSM") and address transition detection ("ATD") provides correct data after a write/erase step, after an erase suspend command is issued or when the device comes out of deep power-down mode. Whenever the WSM takes control of the device the ATD circuits are disabled. When the WSM relinquishes control over the read path it enables ATD by deasserting the disable ATD bar ("DATDB") signal. An internal signal that is a logical inversion of the chip enable bar ("CEB") input is used along with the DATDB signal to generate ATD pulses. Hence, if the user presents a valid address at the address pins with CEB held deasserted when entering the erase suspend mode, the deassertion of the DATDB by the WSM will generate an ATD pulse and valid data will be presented on output pads of the device after an access time. When the device enters the power-down mode, the ATD content addressable memory ("CAM") is powered-down to system power ("VCC") and all internal addresses are forced high. When the device comes out of the power-down mode, the DATDB signal toggles from high (logical one) to low (logical zero). This ensures that an ATD pulse is generated even if the addresses are not toggled.

REFERENCES:
patent: 4592028 (1986-05-01), Konishi
patent: 4803665 (1989-02-01), Kasa
patent: 4843596 (1989-06-01), Miyatake et al.
patent: 4893282 (1990-02-01), Wada et al.
patent: 4916668 (1990-04-01), Matsui

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