Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-12-19
1999-10-05
Yoo, Don Hyun
Static information storage and retrieval
Addressing
Sync/clocking
365202, 36523002, 36523008, G11C 800
Patent
active
059635045
ABSTRACT:
An integrated circuit memory device is designed to perform high speed burst access read and write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit. The address transition detection circuit generates an equilibration control signal between memory access cycles.
REFERENCES:
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4355377 (1982-10-01), Sud et al.
patent: 4484308 (1984-11-01), Lewandowski et al.
patent: 4562555 (1985-12-01), Ouchi et al.
patent: 4567579 (1986-01-01), Patel et al.
patent: 4575825 (1986-03-01), Ozaki et al.
patent: 4603403 (1986-07-01), Toda
patent: 4618947 (1986-10-01), Tran et al.
patent: 4649522 (1987-03-01), Kirsch
patent: 4685089 (1987-08-01), Patel et al.
patent: 4707811 (1987-11-01), Takemae et al.
patent: 4788667 (1988-11-01), Nakano et al.
patent: 4870622 (1989-09-01), Aria et al.
patent: 4875192 (1989-10-01), Matsumoto
patent: 5058066 (1991-10-01), Yu
patent: 5126975 (1992-06-01), Handy et al.
patent: 5267200 (1993-11-01), Tobita
patent: 5268865 (1993-12-01), Takasugi
patent: 5280594 (1994-01-01), Young et al.
patent: 5305284 (1994-04-01), Iwase
patent: 5325330 (1994-06-01), Morgan
patent: 5325502 (1994-06-01), McLaury
patent: 5349566 (1994-09-01), Merritt et al.
patent: 5357469 (1994-10-01), Sommer et al.
patent: 5373227 (1994-12-01), Keeth
patent: 5379261 (1995-01-01), Jones, Jr.
patent: 5392239 (1995-02-01), Margulis et al.
patent: 5410670 (1995-04-01), Hansen et al.
patent: 5452261 (1995-09-01), Chung et al.
patent: 5457659 (1995-10-01), Schaefer
patent: 5487043 (1996-01-01), Furutani et al.
patent: 5499355 (1996-03-01), Krishnamohan et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5568445 (1996-10-01), Park et al.
patent: 5592435 (1997-01-01), Mills et al.
patent: 5598376 (1997-01-01), Merritt et al.
patent: 5610864 (1997-03-01), Manning
patent: 5640364 (1997-06-01), Merrit et al.
patent: 5651130 (1997-07-01), Hinkle et al.
patent: 5652724 (1997-07-01), Manning
patent: 5661695 (1997-08-01), Zagar et al.
patent: 5666321 (1997-09-01), Schaefer
patent: 5668773 (1997-09-01), Zagar et al.
patent: 5675549 (1997-10-01), Ong et al.
patent: 5696732 (1997-12-01), Zagar et al.
patent: 5717654 (1998-02-01), Manning
patent: 5721859 (1998-02-01), Manning
patent: 5729503 (1998-03-01), Manning
patent: 5729504 (1998-03-01), Cowles
patent: 5729709 (1998-03-01), Harness
patent: 5751656 (1998-05-01), Schaefer
patent: 5757703 (1998-05-01), Merritt et al.
patent: 5802010 (1998-09-01), Zagar et al.
""Rossini, Pentium, PCI-ISA, Chip Set"", Symphony Laboratories,, entire book.
"4DRAM 1991", Toshiba America Electronic Components, Inc., pp. A-137--A-159.
"Application Specific DRAM", Toshiba America Electronic Components, Inc., C178, C-260, C 218, (1994).
"Burst DRAM Function & Pinout", Oki Electric Ind., Co., Ltd., 2nd Presentation, Item #619, (Sep. 1994).
"DRAM 1 Meg X 4 DRAM 5VEDO Page Mode", Micron Technology, Inc. 1995 DRAM Data Book, pp. 1-1 thru 1-30.
"Hyper Page Mode DRAM", 8029 Electronic Engineering, 66, Woolwich, London, GB, pp. 47-48, (Sep. 1994).
"Mosel-Vitelic V53C8257H DRAM Specification Sheet", 20 pgs., (Jul. 2, 1994).
"Pipelined Burst DRAM", Toshiba, JEDEC JC 42.3 Hawaii, (Dec. 1994).
"Samsung Synchronous DRAM", Samsung Electronics, pp. 1-16, (Mar. 1993).
"Synchronous DRAM 2 MEG X 8 SDRAM", Micron Semiconductors, Inc., 2-8 to 2-43.
Bursky, D., "Novel I/O Options and Innovative Architectures Let DRAMs Achieve SRAM Performance; Fast DRAMS can be swapped for SRAM Caches", Electronic Design, 41, pp. 55-67, (Jul. 22, 1993).
Gowni, S.P., et al., "A 9NS, 32K X 9, BICMOS TTL Synchronous Cache RAM With Burst Mode Access", Proc.: IEEE Custom Integrated Circuits Conf., pp. 781-786, (Mar. 3, 1992).
Oki, "Burst DRAM Function and Pinout, 128KX16/256KX16", Oki Electric Ind. Co., Ltd., 2nd presentation, Item #619, 1-4, (1994).
Micro)n Technology, Inc.
Yoo Don Hyun
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