Address transition detection circuit

Details Address transition detection circuit Address transition detection circuit

1998-11-24

2000-02-01

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518911, G11C 800, G11C 700

Patent

active

060210893

ABSTRACT:
The present invention relates to an address transition detection (ATD) circuit that generates an address transition detection signal having a prescribed pulse width by detecting a logic transition of an input address bit. The ATD circuit includes a low-to-high first delaying circuit that receives the address bit to delay an output of the address bit of high level but outputs the address bit of low level without a delay. A high-to-low second delaying circuit receives the address bit to output the address bit of high level without a delay, but delays an output of the address bit of low level. A logic gate receives address bit from the first and second delaying circuits output to an address transition detection signal. A feed-back control circuit receives the address transition detection signal to cancel a delaying process of the first and second delaying circuits.

REFERENCES:
patent: 5073872 (1991-12-01), Masuda et al.
patent: 5319607 (1994-06-01), Fujii et al.
patent: 5606269 (1997-02-01), Pontius et al.
patent: 5627796 (1997-05-01), Park et al.
patent: 5696463 (1997-12-01), Kwon
patent: 5734282 (1998-03-01), Choi et al.

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